DTMF Radio Receiver
This project is a PLL synthesized FM radio which can decode DTMF.
The receiving frequency can be set by the PLL circuit from 80-140MHz
The receiver is VERY stable, high sensitivity and easy to build and tune.
The FM receiver can decode DTFM signals from a transmitter and present the
DTMF data on three LED display.
All contribution to this page are most welcome!
The complete background about this project can be found at my "Wife replace" project.
This part is a FM receiver based on a PLL synthesizer UMA1015.
The frequency of the PLL synthesizer is programmed by a PIC processor which also control the DTMF
the LED to display information.
The Audio output from the FM receiver is connected to a DTMF circuit which is specialised to
identify and decode DTMF signals.
If there is a valid DTMF tone the PIC will read the data and present it on the LED display.
Since I have 3 LED I can display 000 to 999 on the display.
So what is the purpose of this cryptically project?
As I said before, this project is a part of my "Wife replace"
project. What this little receiver will do is that it will receive data transmitted from the
"Wife replacer" and present the datainfo on the LED.
The info is actually the signal strength (RSSI) I receive in the "Wife Replacer".
Does is sound blurry, well you should read about the details in my "Wife replacer" project, before
you read this project, and then you will understand the reason of this receiver.
To the left you will find the preamplifier. It is based on a dualgate fet
(You can use almost any dualgate fet).
At Gate 1 we have the antenna input.
L1 and C1 will tune the antenna for best performance. To find perfect antenna match you can
solder the antenna to a tap-point of L1. I can not tell you where to put the tap, you have to
experiment yourself (1-2 turns from ground side should be a good place).
Gate 2 is biased to give high gain. At drain you will find another tuned circuit L2 and C2.
This circuit should also be tuned for best performance.
I have chosen L2 to be a transformer
It has an AL value of 7. With 5 turns primary I will get L= n2*AL
This inductor transform the RF to the secondary side 2 turns which is connected to mixer 1.
In the SA615 you will find an oscillator at pin 3 and 4. This oscillator is connected internally
to mixer 1.
At pin 4 you can find a coil L3 parallel with a capacitor of 3.9pF.
How to make this oscillator voltage controlled?
Parallel with the 3.9pF capacitor you will find a varicap diod.
The capacitans of this diod is dependent of the voltage over it.
So, by applying a voltage to the varicap the internal capacitance will change and so will the
resonance frequency. The purpose of the 10pF serie capacitor is to remove the
By changing the Vtune voltage to the varicap the frequency will slide a few MHz.
At pin 3 you will find a resistor Re. This resistor is added to raise the oscillator current.
A small portion of the oscillator frequency is probed by a dual gate FET. The FET acts as an
amplifier and have a high in impendance. The buffered oscillator signal, then enter the
PLL synthesizer at pin 6.
The mixer 1 mix the RF signal with the oscillator frequency and the IF (Intermediate Frequency) is
455kHz. Two ceramic filters damp all other unwanted frequency and the signal then enter the FM demodulator at pin 14.
To demodulate FM the SA615 use a Quad coil. The audio signal can be found at
pin 9 and the RSSI signal can be found at pin 7.
I will now show you some measurement about the demodulator in the SA615 and its behaviour.
The two graphs above will show you the behaviour of the FM demodulator in the SA615 circuit.
The first graph to the left show you the signal recovery from the FM (frequency modulation).
The X-axle show you the modulating frequency and the Y-axle show you the output AC voltage.
In that graph, I will only draw the positive frequency deviation, since the negative has the same
behaviour but gives a negative output signal.
If you have constant frequency of 455kHz and no modulation (variation) the AC output
signal will be 0V.
If the frequency change + 5 kHz up from 455kHz (red arrow) the output will go to + 65mV peak.
The same behaviour happens if the frequency drop 5kHz from 455kHz, then the output signal will be -65mV peak.
So by changing the frequency around the 455kHz the output AC signal will vary and restore the audio signal.
Above 10kHz you will see a strange behaviour of the output, this is due to the 455kHz filter. The filter is
sharp and above 10kHz the filter start to reject the signal and the demodulation won't be pretty.
Now, lets have a look at the other graph. This one will show you the DC output signal as a function of the input frequency
to the demodulator. The input signal should be 455kHz and in that case the DC is about 1.7V.
If the input signal would be modulated around another frequency the DC output would not be 1.7V.
If the audio signal is modulated around 465kHz the DC output would be about 1.0V.
Well, this DC signal is sometimes used to work as an AFC meaning (Automatic Frequency Control).
Some receivers probe this DC voltage and regulate the receiver oscillator so the receiver lock to 455kHz.
This is very helpfully when tuning manually. When you tune, you only need to get close to the RF
frequency, and then the AFC will correct the oscillator and lock the receiver to the RF signal.
If you want all details about AFC, you can read it in my AFC project.
In this project I use a bit different PLL synthesizer. The reason I choose this one is because I
found 4 of them in some cordless phones I found in a container.
Let's have a look at the schematic. A Dualgate FET is used as a buffer from the oscillator.
This buffer amplifies the signal and prevent glitches and noise from the PLL to go back into the
oscillator. The pin 6 is the input pin for RF signal.
The UMA1015 PLL is programmed in serially way and use 3 pins for it (Latch, Clock, Data).
I advice you to read the datasheet to find the details about the internal register of this circuit.
I did find this circuit easy to use and understand. Pin 18 has a resistor connected to ground.
This resistor set the current which the PLL use with the phase comparator and charge pump.
In my construction this PLL will lock the PLL to a constant frequency so there is no
critical timing to take care of, as it would be if the PLL should jump from
one frequency to another. A external crystal module is used as reference frequency.
In this construction I use a 12.8MHz module as reference frequency. The PLL has an output to generate the tuning
You can find this output at pin 3. Some capacitor and resistor form a filter and
this voltage is then connected back to the varicap at the oscillator.
The basic function of the PLL is that the frequency from the oscillator is divided with a
programmed ration and compared with the fixed frequency which also is divided with another
The phase of the two signals is compared and generate a DC voltage at the PD-output.
This DC voltage will regulate the main RF oscillator until the signal in the PLL has the same phase.
This will occur when both signals in the PLL has the same phase.
The PLL has now locked the RF oscillator to the desired frequency.
If you want more detailed information about PLL synthesizer and phase comparators,
I suggest you read the zipped document at bottom or search the internet for PLL synthesizer.
Building and testing
Start your project with the SA615 circuit. Add the oscillator buffer and make sure you got
the oscillator working and that you have a nice signal out of the buffer. Add also the varicap
and connect pin 3 of the UMA1015 to ground. This simulate that the Vtune is 0V.
If you now connect pin3 to +5V, you simulate the Vtune to be +5V and you should see a
distinct change of the oscillating frequency.
I advice you to use a frequency counter, or to build my wireless frequency counter
it helped me a lot.
You could connect Vtune to a variable pot and thereby have a manually tuned receiver.
Now we have come to the digital part. Add the PLL circuit and the PIC16F870.
The UMA1015 is a bit tricky to solder so don't party the day before you solder it *smiling*
I tune my unit by changing the size of coil L3. You can probe the Vtune with a DC voltmeter and
when the DC is 0V the oscillator frequency is to high and when the DC is +5V the oscillator
frequency is to low.
Finally you end up somewhere between 0 and 5V and in that area the PLL lock the oscillator
to the desired frequency.
C1 and C2 is tuned by ear. I connected a high impedance audio amplifier and listened to the
incoming DTMF signal and tuned the two capacitor until I got the best signal and sensitivity.
The receiver need 3 DTMF tones. The tone should be 50mS long and a after each tone it should be a 50mS long pause, that is all!
This project is explaining how you can receive DTMF singnal and present them on 3 LEDs.
Here I have given you the basic structure of a PLL synthesized receiver.
The SA615 ciruit is a very good circuit and hopefully it will stay on the market for some years,
so I advice you to start using it in your projects.
You can always mail me if there is anything unclear.
I wish you good luck with your projects and thanks for visit my page.